1. Field of the Invention
The present invention relates to a test that is performed by causing a simulated failure to occur at a printed circuit board mounted to an information processor.
2. Description of the Related Art
Hitherto, testing of an information processor has been performed by causing a simulated failure to occur as a result of bringing a probe into contact with, for example, a predetermined component on a printed circuit board mounted to the information processor. Many information processors have a plurality of printed circuit boards mounted thereto in the form of layers. The probe is inserted between printed circuit boards to bring the probe into contact with, for example, components on the printed circuit boards.
However, since the probe that is inserted between the printed circuit boards has a long lead wire, an evaluation test of the information processor cannot be efficiently carried out.
Accordingly, a printed-circuit-board testing device for efficiently performing an evaluation test of an information processor is disclosed in Japanese Patent Application No. 2004-234837. The printed-circuit-board testing device according to this document performs tests on printed circuit boards, which are mounted to the information processor in the form of layers, by efficiently causing a simulated failure to occur at the printed circuit boards. A guide panel for establishing ground is disposed between the printed circuit boards. An arm having a probe is inserted between the printed circuit board to be tested and the guide panel. The test is performed by causing a simulated failure to occur as a result of bringing the probe into contact with a predetermined via hole and/or land of the printed circuit board and establishing ground with respect to the guide panel.
The testing device disclosed in Japanese Patent Application No. 2004-234837 performs testing by controlling the position of the probe on the basis of positional information of the predetermined via hole and/or land.
FIG. 1 is a conceptual diagram related to testing of a printed circuit board in a related art.
Electronic components 108, 109, 110, and 111 are mounted to a printed circuit board 103. A land 105 is also provided on the printed circuit board 103. A probe is brought into contact with the land 105 to cause a simulated failure to occur. The probe is provided at an arm 101 so that it can protrude from the arm 101.
After positioning the arm 101 on the basis of positional information of the land 105, the probe protrudes from the arm 101 and comes into contact with the land 105. When the probe comes into contact with the land 105, a coma, disposed at a surface of the arm 101 that is opposite to the surface of the arm 101 from which the probe protrudes, is grounded to a guide panel 104 due to reaction pressure that is generated when the probe contacts the land 105, so that a simulated failure occurs. Here, the probe and the coma are not illustrated, and the printed circuit board 103 is parallel to the guide panel 104.
When a printed circuit board is to be tested, ideally, the arm 101 is parallel to the printed circuit board 103.
However, the arm 102 is not parallel to the printed circuit board 103. When a tilt angle θ106 exists between the arm 102 and the printed circuit board 103, an error δ107 is occurs. This prevents the probe from precisely contacting the land 105. Therefore, the testing that is performed by precisely causing a simulated failure to occur cannot be reliably performed.
To precisely perform the testing of the printed circuit board 103, the tilt angle θ106 between the arm 102 and the printed circuit board 103 needs to be brought as close as possible to zero.
At present, the printed circuit board 103 and the arm 102 are visually brought parallel to each other, so that considerable time is used to bring the printed circuit board 103 and the arm 102 parallel to each other.